module top (
  input clk, 
  output LED0,
  output LED1,
  output LED2,
  output LED3,
  output LED4,
  output LED5,
  output LED6,
  output LED7
);
  reg [13:0] vLEDs = 1;
  always @(posedge clk)
    begin
      vLEDs <= { vLEDs[12:0], vLEDs[13] };
      LED0 <= vLEDs[7];
      LED1 <= vLEDs[6] | vLEDs[8];
      LED2 <= vLEDs[5] | vLEDs[9];
      LED3 <= vLEDs[4] | vLEDs[10];
      LED4 <= vLEDs[3] | vLEDs[11];
      LED5 <= vLEDs[2] | vLEDs[12];
      LED6 <= vLEDs[1] | vLEDs[13];
      LED7 <= vLEDs[0];
    end
endmodule