'' PSRAM 8MB-Treiber con _CLKMODE = XTAL1 + PLL16X _XINFREQ = 5_000_000 spi_in =%0000 'Datenleitungen als Eingang spi_out =%1111 'Datenleitungen als Ausgang CS =0 'CS 1 SIO0 =8 'MISO 5 SIO1 =9 '2 SIO2 =10 '3 SIO3 =11 'MOSI 7 CLK =1 'CLK 6 CNTRL =%11 'CS und CLK als Ausgang baud =19200 {{ PSRAM64H driver. Für PSRAM-Chip 8M (64Mbit) Vdd(+3.3V) Vdd(+3.3V)   │ PSRAM64H │  │ │ ┌────────────────┐ │ 0.1µF P0 ───┻─┤1 /CS Vcc 8├───┻────── Vss P9 ─────┤2 SIO1 SIO3 7├────────── P11 P10 ─────┤3 SIO2 CLK 6├────────── P1 ┌──┤4 GND SIO0 5├────────── P8  └────────────────┘ Vss Pullup resistors are 10K }} obj ser :"FullDuplexSerialExtended" var PUB Main|adr,putbyte,getbyte,fails ser.start(31, 30,0,baud)'0, baud) 'serielle Schnittstelle starten ser.str(string("PSRAM-Test",13)) dira[CS..CLK]:=CNTRL 'CS und CLK = Output dira[SIO3..SIO0]:=spi_in 'SIO0-3 = Input fails:=0 reset 'Reset Ram SPI2SQI 'in den SQI Mode schalten repeat adr from $0 to $7FFFFF RamByteWrite(adr,PutByte) Getbyte:=RamByteRead(adr) if (adr // $1000) == 0 ser.hex(adr,6) ser.tx(32) ser.str(string("-OK-")) ser.tx(13) if PutByte<>GetByte ser.str(string("fail at Address")) ser.hex(adr,6) ser.tx(32) ser.dec(PutByte) ser.tx(32) ser.dec(GetByte) ser.tx(13) fails++ PutByte++ if putbyte>255 putbyte:=0 Ser.str(string("RAM-Test abgeschlossen",13)) ser.str(string("Fehler:")) ser.dec(fails) ser.tx(13) PUB ClockStrobe outa[CLK]~~ outa[CLK]~ PUB SQIAddress(adr) outa[sio3..sio0]:=adr>>20 & $F '// Output Address 23 To 20; ClockStrobe '// Latch Address 23 To 20; outa[sio3..sio0]:=adr>>16 & $F '// Output Address 19 To 16 ClockStrobe '// Latch Address 19 To 16 outa[sio3..sio0]:=adr>>12 & $F '// Output Address 15 To 12 ClockStrobe '// Latch Address 15 To 12 outa[sio3..sio0]:=adr>>8 & $F '// Output Address 11 To 8 ClockStrobe '// Latch Address 11 To 8 outa[sio3..sio0]:=adr>>4 & $F '// Output Address 7 To 4 ClockStrobe '// Latchh Address 7 To 4 outa[sio3..sio0]:=adr & $F '// Output Address 3 To 0 ClockStrobe '// Latch Address 3 to 0 PUB SPI2SQI '// Force RAM Into SQI Mode 0x38 dira[SIO0] :=1 outa[CS] :=0 outa[SIO0] :=0 '// Set Data Output Low ClockStrobe '// Latch Bit7=0 ClockStrobe '// Latch Bit6=0 outa[SIO0] :=1 '// Set Data Output HIGH ClockStrobe '// Latch Bit5=1 ClockStrobe '// Latch Bit4=1 outa[SIO0] :=0 '// Set Data Output Low ClockStrobe '// Latch Bit3=0 outa[SIO0] :=1 '// Set Data Output HIGH ClockStrobe '// Latch Bit2=1 outa[SIO0] :=0 '// Set Data Output Low ClockStrobe '// Latch Bit1=0 outa[SIO0] :=1 '// Set Data Output HIGH ClockStrobe '// Latch Bit0=1 dira[SIO3..SIO0] :=SPI_IN '// Set D0 As Input outa[CS] :=1 '// Disable RAM Chip PUB SQIByteRead(adr):wert|a,b 'QPI READ-Byte $0B(%0000_1011 slow) or $EB(%1110_1011 fast) für Spin reicht slow (bis 66MHz) outa[CS] :=0 '// Enable RAM Chip outa[SIO3..SIO0] :=%0000 '$0B '%1110'// Output Upper Nibble Command $EB dira[SIO3..SIO0] :=SPI_OUT '// Set D3,D2,D1,D0 As Outputs ClockStrobe '// Latch Upper Nibble Command outa[SIO3..SIO0] :=%1011 '// Output Lower Nibble Command ClockStrobe '// Latch Lower Nibble Command SQIAddress(adr) '// Strobe Out The Address dira[SIO3..SIO0] :=SPI_IN repeat 4 ClockStrobe '// Strobe wert :=ina[SIO3..SIO0] << 4 '// Grab Upper Nibble From SRAM ClockStrobe '// Ack Upper Nibble wert :=wert + ina[SIO3..SIO0] '// Grab Lower Nibble From SRAM ClockStrobe '// Ack Lower Nibble outa[CS] :=1 '// Disable RAM Chip return wert PUB SQIByteWrite(adr,c)|l1,l2 'QPI WRITE-Byte $02 (%0000_0010) or $38 (%0011_1000) outa[CS] :=0 '// Enable RAM Chip outa[SIO3..SIO0] :=%0011 '// Output Upper Nibble Command dira[SIO3..SIO0] :=SPI_OUT '// Set D3,D2,D1,D0 As Outputs ClockStrobe '// Latch Upper Nibble Command outa[SIO3..SIO0] :=%1000 '// Output Lower Nibble Command ClockStrobe '// Latch Lower Nibble Command SQIAddress(adr) '// Strobe Out The Address outa[SIO3..SIO0] :=c >> 4 '// Output Data Upper Nibble ClockStrobe '// Latch The Data Upper Nibble outa[SIO3..SIO0] :=c & $F '// Output Data Lower Nibble ClockStrobe '// Latch The Data Lower Nibble dira[SIO3..SIO0] :=SPI_IN '// Set D3,D2,D1,D0 As Inputs outa[CS] :=1 '// Disable RAM Chip PUB RamByteRead(adr):wert 'dira:=SPI_IN wert:=SQIByteRead(adr) return wert PUB RamByteWrite(adr,c) ' dira:=SPI_IN SQIByteWrite(adr,c) PUB Reset dira[SIO0] :=1 outa[CLK] :=0 outa[CS] :=0 outa[SIO0] :=0 '// Set Data Output HIGH ClockStrobe '// Latch Bit6=0 outa[SIO0] :=1 '// Set Data Output HIGH ClockStrobe '// Latch Bit5=1 ClockStrobe '// Latch Bit5=1 outa[SIO0] :=0 '// Set Data Output HIGH ClockStrobe '// Latch Bit4=0 ClockStrobe '// Latch Bit3=0 outa[SIO0] :=1 '// Set Data Output HIGH ClockStrobe '// Latch Bit5=1 ClockStrobe '// Latch Bit5=1 outa[SIO0] :=0 '// Set Data Output HIGH ClockStrobe '// Latch Bit4=0 dira[SIO0] :=0 '// Set D0 As Input outa[CS] :=1 '// Disable RAM Chip dira[SIO0] :=1 outa[CS] :=0 outa[SIO0] :=1 '// Set Data Output Low ClockStrobe '// Latch Bit7=1 outa[SIO0] :=0 '// Set Data Output HIGH ClockStrobe '// Latch Bit6=0 ClockStrobe '// Latch Bit6=0 outa[SIO0] :=1 '// Set Data Output HIGH ClockStrobe '// Latch Bit5=1 ClockStrobe '// Latch Bit5=1 outa[SIO0] :=0 '// Set Data Output HIGH ClockStrobe '// Latch Bit4=0 ClockStrobe '// Latch Bit3=0 outa[SIO0] :=1 '// Set Data Output Low ClockStrobe '// Latch Bit2=1 dira[SIO0] :=0 '// Set D0 As Input outa[CS] :=1 '// Disable RAM Chip