384KB hub RAM
256KB ROM for on-chip development
64 I/O pins
Pipelined execution, 160MHz = 160MIPS
Multi-threading within cogs
Code protect encryption in EEPROM
CORDIC subsystem in each cog
Hardware divide (multi-cycle) and multiply (single-cycle)
Perspective-correct texture mapping with lighting and alpha-blending in each cog with 5:5:5 RGB representation
Every I/O pins has: ADC, DAC, video DAC, comparator,oscillator function, schmitt input/osc, low EMI mode, variousstrong/weak/high-z H/L output modes